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| 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 1998 Revised October 2004 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The VCX16601 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The VCX16601 is designed for low voltage (1.4V to 3.6V) VCC applications with I/O capability up to 3.6V. The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (A to B, B to A) 2.9 ns max for 3.0V to 3.6V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Static Drive (IOH/IOL) 24 mA @ 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74VCX16601GX (Note 2) 74VCX16601MTD (Note 3) Package Number BGA54A (Preliminary) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 2004 Fairchild Semiconductor Corporation DS500126 www.fairchildsemi.com 74VCX16601 Connection Diagrams Pin Assignment for TSSOP Pin Descriptions Pin Names OEAB, OEBA LEAB, LEBA CLKAB, CLKBA Description Output Enable Inputs (Active LOW) Latch Enable Inputs Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A1-A18 B1-B18 Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs FBGA Pin Assignments 1 A B C D E F G H J A2 A4 A6 A8 A10 A12 A14 A16 A17 2 A1 A3 A5 A7 A9 A11 A13 A15 A18 3 4 5 B1 B3 B5 B7 B9 B11 B13 B15 B18 6 B2 B4 B6 B8 B10 B12 B14 B16 B17 OEAB CLKENAB LEAB VCC GND GND GND VCC OEBA CLKAB VCC GND GND GND VCC CLKBA LEBA CLKENBA Truth Table (Note 4) Inputs CLKENAB X Pin Assignment for FBGA X X H H L L L L OEAB LEAB CLKAB H L L L L L L L L X H H L L L L L L X X X X X An X L H X X L H X X Outputs Bn Z L H B0 (Note 5) B0 (Note 5) L H B0 (Note 5) B0 (Note 6) L H (Top Thru View) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 5: Output level before the indicated steady-state input conditions were established. Note 6: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. www.fairchildsemi.com 2 74VCX16601 Logic Diagram 3 www.fairchildsemi.com 74VCX16601 Absolute Maximum Ratings(Note 7) Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-Stated Outputs Active (Note 8) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5 to VCC + 0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C Recommended Operating Conditions (Note 9) Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V VCC = 1.4V to 1.6V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 7: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 8: IO Absolute Maximum Rating must be observed. Note 9: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. 1.4V to 3.6V -0.3V to 3.6V 0V to VCC 0.0V to 3.6V 24 mA 18 mA 6 mA 2 mA -40C to +85C DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VIL LOW Level Input Voltage 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA IOH = -100 A IOH = -6 mA IOH = -12 mA IOH = -18 mA IOH = -100 A IOH = -6 mA IOH = -100 A IOH = -2 mA 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2.0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 V Min 2.0 1.6 0.65 x VCC 0.65 x VCC 0.8 0.7 0.35 - VCC 0.35 - VCC V V Max Units www.fairchildsemi.com 4 74VCX16601 DC Electrical Characteristics Symbol VOL Parameter LOW Level Output Voltage (Continued) VCC (V) 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 2.7 - 3.6 1.4 - 3.6 0 1.4 - 3.6 1.4 - 3.6 2.7 - 3.6 Conditions IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 24 mA IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 100 A IOL = 6 mA IOL = 100 A IOL = 2 mA Min Max 0.2 0.4 0.4 0.55 0.2 0.4 0.6 0.2 0.3 0.2 0.35 5.0 10.0 10.0 20.0 20.0 750 Units V II IOZ IOFF ICC ICC Input Leakage Current 3-STATE Output Leakage Power Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0V VI 3.6V 0V VO 3.6V VI = VIH or VIL 0V (VI, VO) 3.6V VI = VCC or GND VCC (VI, VO) 3.6V (Note 10) VIH = VCC - 0.6V A A A A A Note 10: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCX16601 AC Electrical Characteristics (Note 11) Symbol fMAX Parameter Maximum Clock Frequency CL = 30 pF Conditions VCC (V) 3.3 0.3 2.5 0.2 1.8 0.15 CL = 15 pF tPHL tPLH Propagation Delay Bus-to-Bus CL = 15 pF, RL = 2k tPHL tPLH Propagation Delay Clock-to-Bus CL = 15 pF, RL = 500 tPHL tPLH Propagation Delay LE-to-Bus CL = 15 pF, RL = 500 tPZL tPZH CL = 15 pF, RL = 2k tPLZ tPHZ CL = 15 pF, RL = 2k tS Setup Time CL = 30 pF, RL = 500 Output Disable Time CL = 30 pF, RL = 500 Output Enable Time CL = 30 pF, RL = 500 CL = 30 pF, RL = 500 CL = 30 pF, RL = 500 CL = 30 pF, RL = 500 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 CL = 15 pF, RL = 500 tH Hold Time CL = 30 pF, RL = 500 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 CL = 15 pF, RL = 500 tW Pulse Width CL = 30 pF, RL = 500 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 CL = 15 pF, RL = 500 tOSHL tOSLH Output to Output Skew (Note 12) CL = 15 pF, RL = 2k Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). TA = -40C to + 85C Min 250 200 100 80.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 1.5 1.5 2.5 3.0 1.0 1.0 1.0 2.0 1.5 1.5 4.0 4.0 0.5 0.5 0.75 1.5 2.9 3.5 7.0 14.0 3.5 4.4 8.8 17.6 3.5 4.4 8.8 17.6 3.8 4.9 9.8 19.6 3.7 4.2 7.6 15.2 Max Units Figure Number MHz ns Figures 1, 2 Figures 7, 8 Figures 1, 2 Figures 7, 8 Figures 1, 2 Figures 7, 8 Figures 1, 3, 4 Figures 7, 9, 10 Figures 1, 3, 4 Figures 7, 9, 10 ns ns ns ns ns Figure 6 ns Figure 6 ns Figure 5 1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1 CL = 30 pF, RL = 500 ns www.fairchildsemi.com 6 74VCX16601 Dynamic Switching Characteristics Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V V Units Capacitance Symbol CIN CI/O CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VI = 0V or VCC VCC = 1.8V, 2.5V, or 3.3V VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz VCC = 1.8V, 2.5V or 3.3V Conditions TA = +25C 6.0 7.0 20.0 Units pF pF pF 7 www.fairchildsemi.com 74VCX16601 AC Loading and Waveforms (VCC 3.3V 0.3V to 1.8V 0.15V) FIGURE 1. AC Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open 6V at VCC = 3.3V 0.3V; VCC x 2 at VCC = 2.5V 0.2V; 1.8V 0.15V GND FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol Vmi Vmo VX VY FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V www.fairchildsemi.com 8 74VCX16601 AC Loading and Waveforms (VCC 1.5V 0.1V) TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VCC x 2 at VCC = 1.5 0.1V GND FIGURE 7. AC Test Circuit FIGURE 8. Waveform for Inverting and Non-inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 1.5V 0.1V VCC/2 VCC/2 VOL + 0.1V VOH - 0.1V 9 www.fairchildsemi.com 74VCX16601 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) www.fairchildsemi.com 10 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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